Comment by periblepsis on Verilog Non-blocking and Blocking is logically confusing

I think it is nicely written. But there's a few subtle bits. One is that simulation \$\ne\$ synthesis. And the sheet starts out mentioning simulation and then heads over and shows a possible synthesis to make their point. Slide 4, right side: when clk goes hi, q1 gets assigned in. But inside that block, to assign q2 to the value of q1 all synthesis needs to do is just wire the two together. Etc. So one latch. Left side: in this case, synthesis knows it has to collect up all three values first and move things over all at the same time with clk. That means 3 latches.