The basic idea will be something like this:
simulate this circuit– Schematic created using CircuitLab
It's not a complete design and I used \$5\:\text{V}\$ here. (I'd recommend keeping the \$10\,\text{mA}\$ current sink but adjust the biasing as appropriate for other rail voltages.)
The duty cycle won't be a perfect 50%.
Using very low Q, only 2000 for this example, LTspice shows this (the outputs are taken from the two collectors):
(Higher Q works well, of course.)
This would not be a final design. If for no other reason then because the output likely needs buffering before it drives some other circuit. But it is a demonstration of the behavioral topology to use as a basis.