Comment by periblepsis on FPGA: Must clock crossing FIFO be made up of BRAM?

I like the ZipCPU site for educating myself on FPGA coding. There's this link on Crossing clock domains with an Asynchronous FIFO and this link on Minimizing FPGA Resource Utilization, which has a section on using block RAM. I'm only suggesting them as worthy of a good read that may help. Not as a solution to your question (or I would have added an answer and referred to those pages.)