If I write software for a mixed language toolchain, capable of sufficient analysis to generate not one but several runtime CPU architectures and control software, even including self-modifying controlling microstores, to target some limited hardware box of FPGAs (for example, but not so limited), and it generates several kinds of division instructions (say it decides I need a 48-bit/24-bit divisor, plus a 12-bit/6-bit divisor, for part of the application run) then what is the meaning of your question?
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