I thought I'd just suggest something for you to consider in the future. It has just enough features to be generally useful.
keypad and scan driver
Here's what I'd start with, with respect to the input pad:
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The columns and rows have pull-ups. I'd probably use \$2.2\:\text{k}\Omega\$ resistors for this. The 7445 BCD decoder shown above is designed with outputs sporting high-breakdown transistors (\$30\:\text{V}\$) that are able to sink \$80\:\text{mA}\$. (Keeping in mind that with the right set of simultaneous key-presses it is technically possible for five of the pull-ups to be active at once.)
The above schematic block accepts a binary input at \$G_0\$ and \$G_1\$. I have wired it above to scan the columns sequentially when provided with the output from a 2-bit twisted-ring Johnson counter.
column scanning
I tend to prefer a twisted ring Johnson counter (only one bit changes per state change), other things being equal.
I also like the 7476 over the 7474, perhaps in part because I've used a lot of them over the years and perhaps also in part because they sport async clear and set inputs. In this case, I've added a POR (power-on reset) feeding these JK FFs so that they come up in a known state. It's not necessary (who cares?), but I'm just being pedantic here.
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A 555 timer (CMOS or otherwise) is shown providing the clock for scanning.
At this point, there are three ICs so far: 555 timer, 7445, and 7476. And these together will scan the columns and generate outputs \$C_1\dots C_4\$ and \$R_1\dots R_4\$, which can be captured if any of \$R_1\dots R_4\$ goes LOW.
recognizing a keypress
Speaking of which, the following circuit uses Schmitt trigger 4-in NAND gates to provide a latch enable output (and its complement) whenever any of \$R_1\dots R_4\$ goes LOW.
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\$LE\$ will be used by the 8-bit latch (coming up.) \$\overline{LE}\$ will be used by a data avail FF (also coming up.)
data available signal
It helps to provide a signal to indicate when a keypress has been captured. I'd use this:
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It's simple enough. However, depending upon how things power up (I'm not feeding this the POR signal) it may falsely signal a data available output. When first starting up, it's a good idea to just toggle the \$CLR\$ (which should normally be kept HIGH and toggled LOW to clear the data available signal.)
row and column data latch
This is pretty easy and accepts a rising edge on \$LE\$ to trigger the latching event. This will capture both the row and the column. (The active row and active column will be read as LOW, with the remaining bits hopefully HIGH.)
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completed system
All put together, it's this:
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It's been some time since I've built one of these (decades and decades ago), back when using an MCU wasn't really an option and things had to be done this way. (And the above isn't what I built, then.)
Today, of course, an MCU would wipe the floor of something like what I've presented above. You should definitely considering using an MCU, instead. But perhaps you need the above to convince yourself of that. So there it is.
Best wishes.
P.S. Feel free to add those optos. I left that part for you.