Thanks for the discussion. In keeping with your idea of using 74373. But the following uses the edge-type 74374 (possibly fewer update clocks required -- especially if you can skew the clock slightly -- but check just in case):
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The protocol would be the following:
- Clock \$W_{_\text{HI}}\$ with \$P_3\dots P_0=0\$ and \$D_1 D_0\$ set to the upper 2 bits of the data to be written.
- Clock \$W_{_\text{LO}}\$ with \$D_5\dots D_0\$ set to the lower 6 bits of the data to be written.
- Clock \$W_{_\text{HI}}\$, with \$D_1 D_0\$ still set to the upper 2 bits of the data to be written, but now also clocking one of \$P_3\dots P_0\$ depending on the desired output port to update.
For example, to write 0xA5 to \$OUT_2\$ use: 0x82, 0x65, 0x92, 0x00. Or, to write 0xA5 to \$OUT_2\$ and 0xE7 to \$OUT_0\$ use: 0x82, 0x65, 0x92, 0x83, 0x67, 0x87, 0x00. (That last 0x00 is just to put everything back to rest.)
Here's a longer example showing the above two port writes plus another two so that all four port outputs are set:
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That's it. Every three writes updates a port. Not too shabby.
As I said, I'd probably go with 74374's instead of 74373's and add some clock skew. The transparent mode otherwise requires an extra cycle, which I'd rather avoid.
